Course Overview
The Workshops will help you to:
Understand the intricate workings of Intel FPGA architectures, garnering a robust understanding that sets the foundation for successful FPGA design. The training walks you through the detailed nuances of the tool flows of these leading FPGA technologies, ensuring a seamless design experience. You will be introduced to writing synthesizable codes, which is the cornerstone of any FPGA project. Harness the power of in-built libraries, understanding their intricate functionalities, and leverage them for efficient FPGA designs. Additionally, the training accentuates the crucial stages of downloading code into FPGA and offers hands-on experience on its debugging features. By the end of this course, be well-equipped with the expertise to tackle any FPGA challenge, ensuring optimal designs and smooth project executions.
Who Should Attend
Engineers and technicians who are involved in the design, implementation and test of digital system design using FPGA.
Methodology
Seminar consists of 2 days’ training workshops. The course will be delivered through a mixture of classroom lectures and hands-on laboratory exercises using industry standard EDA tools and FPGA development board.
The training can be tailored for beginners, intermediate or advanced level, and can be delivered on-site, online or hybrid.
Course Content
Topic 1: Introduction to FPGA
- Cyclone/Stratix device Architecture
- Introduction to Quartus II
- Creating Project
- Using Editor & Design Entry
Topic 2: Analysis and Elaboration
- I/O Assignment
- Configure voltage for I/0
- I/O Assignment Analysis
- Synthesis
- Netlist Viewer
Topic 3: Introduction to HDL
Hands-on laboratory
Topic 4: Constraints
- Importance of Constraints in Design
- Clock frequency
- Asynchronous & Synchronous Design
- False Path/Multicycle path
Topic 5: Placing Design in FPGA
- Fitter (Place & Route)
- Chip Planner
- Assembler (Generating Programming file)
- Downloading Design in FPGA
Topic 6: Static Time analysis (STA) – for intermediate/advanced level only
- Running TimeQuest Timing Analyzer
- Understanding reports
- Understand setup/hold violation & failing paths
- Constraining and understanding TCL Commands
Hands-on laboratory
